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maxim integrated products 1 general description the MAX5816 4-channel, low-power, 12-bit, voltage- output digital-to-analog converter (dac) includes output buffers and an internal reference that is selectable to be 2.048v, 2.500v, or 4.096v. the MAX5816 accepts a wide supply voltage range of 2.7v to 5.5v with extremely low power (3mw) consumption to accommodate most low- voltage applications. a precision external reference input allows rail-to-rail operation and presents a 100k i (typ) load to an external reference. the MAX5816 has an i 2 c-compatible, 2-wire interface that operates at clock rates up to 400khz. the dac output is buffered and has a low supply current of less than 250 f a per channel and a low offset error of q 0.5mv (typ). on power-up, the MAX5816 resets the dac outputs to zero, providing additional safety for applications that drive valves or other transducers which need to be off on pow - er-up. the internal reference is initially powered down to allow use of an external reference. the MAX5816 allows simultaneous output updates using software load com - mands. multiple devices can simultaneously be updated using software load command in combination with the broadcast id. the MAX5816 is available in a 10-pin tdfn package and is specified over the -40 n c to +125 n c temperature range. applications programmable voltage and current sources gain and offset adjustment automatic tuning and optical control power amplifier control and biasing process control and servo loops portable instrumentation data acquisition benefits and features s four high-accuracy dac channels ? 12-bit accuracy without adjustment ? 1 lsb inl buffered voltage output ? guaranteed monotonic over all operating conditions ? independent mode settings for each dac s three precision selectable internal references ? 2.048v, 2.500v, or 4.096v s internal output buffer ? rail-to-rail operation with external reference ? 4.5s settling time ? outputs directly drive 2k i loads s small 3mm x 3mm 10-pin tdfn package s wide 2.7v to 5.5v supply range s fast 400khz i 2 c-compatible, 2-wire serial interface s power-on-reset to zero-scale dac output s three software-selectable power-down output impedances ? 1k i , 100k i , or high impedance 19-6149; rev 0; 2/12 ordering information appears at end of data sheet . functional diagram addr sda scl outa buffer por v dd gnd dac control logic power-down ref outb outc outd i 2 c serial interface 1ki 100ki code load clear/ reset clear / reset code register dac latch 8- /1 0- / 12-bit dac 1 of 4 dac channels internal reference/ external buffer MAX5816 for related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX5816.related MAX5816 ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
maxim integrated products 2 v dd to gnd ............................................................. -0.3v to +6v out_, ref to gnd ....0.3v to the lower of (v dd + 0.3v) and +6v scl, sda to gnd ................................................... -0.3v to +6v addr to gnd ........ -0.3v to the lower of (v dd + 0.3v) and +6v continuous power dissipation (t a = +70 n c) tdfn (derate at 24.4mw/ n c above 70 n c) ............. 1951.2mw maximum continuous current into any pin .................... q 50ma operating temperature .................................... -40 n c to +125 n c storage temperature ....................................... -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) .................................... +260 n c tdfn junction-to-ambient thermal resistance ( ja ) ......... 41 n c/w junction-to-case thermal resistance ( jc ) ................. 9 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 2.7v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units dc performance (note 3) resolution and monotonicity n 12 bits integral nonlinearity (note 4) inl -1 q 0. 5 +1 lsb differential nonlinearity (note 4) dnl -1 q 0.2 +1 lsb offset error (note 5) oe -5 q 0.5 +5 mv offset error drift q 10 f v/ n c gain error (note 5) ge -1.0 q 0.1 +1.0 %fs gain temperature coefficient with respect to v ref q 3.0 ppm of fs/ n c zero-scale error 0 10 mv full-scale error with respect to v ref -0.5 +0.5 %fs dac output characteristics output voltage range (note 6) no load 0 v dd v 2k i load to gnd 0 v dd - 0.2 2k i load to v dd 0.2 v dd ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 3 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units load regulation v out = v fs /2 v dd = 3v q 10%, |i out | p 5ma 300 f v/ma v dd = 5v q 10%, |i out | p 10ma 300 dc output impedance v out = v fs /2 v dd = 3v q 10%, |i out | p 5ma 0.3 i v dd = 5v q 10%, |i out | p 10ma 0.3 maximum capacitive load handling c l 500 pf resistive load handling r l 2 k i short-circuit output current v dd = 5.5v sourcing (output shorted to gnd) 30 ma sinking (output shorted to v dd ) 50 dc power-supply rejection v dd = 3v q 10% or 5v q 10% 100 f v/v dynamic performance voltage-output slew rate sr positive and negative 1.0 v/ f s voltage-output settling time ? scale to ? scale, to p 1 lsb 4.5 f s dac glitch impulse major code transition 2 nv*s channel-to-channel feedthrough (note 7) external reference 3.5 nv*s internal reference 3.3 digital feedthrough code = 0, all digital inputs from 0v to v dd 0.2 nv*s power-up time startup calibration time (note 8) 200 f s from power-down 50 f s output voltage-noise density (dac output at midscale) external reference f = 1khz 90 nv/ hz f = 10khz 82 2.048v internal reference f = 1khz 112 f = 10khz 102 2.5v internal reference f = 1khz 125 f = 10khz 110 4.096v internal reference f = 1khz 160 f = 10khz 145 ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 4 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units integrated output noise (dac output at midscale) external reference f = 0.1hz to 10hz 12 f v p-p f = 0.1hz to 10khz 76 f = 0.1hz to 300khz 385 2.048v internal reference f = 0.1hz to 10hz 14 f = 0.1hz to 10khz 91 f = 0.1hz to 300khz 450 2.5v internal reference f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 99 f = 0.1hz to 300khz 470 4.096v internal reference f = 0.1hz to 10hz 16 f = 0.1hz to 10khz 124 f = 0.1hz to 300khz 490 output voltage-noise density (dac output at full scale) external reference f = 1khz 114 nv/ hz f = 10khz 99 2.048v internal reference f = 1khz 175 f = 10khz 153 2.5v internal reference f = 1khz 200 f = 10khz 174 4.096v internal reference f = 1khz 295 f = 10khz 255 integrated output noise (dac output at full scale) external reference f = 0.1hz to 10hz 13 f v p-p f = 0.1hz to 10khz 94 f = 0.1hz to 300khz 540 2.048v internal reference f = 0.1hz to 10hz 19 f = 0.1hz to 10khz 143 f = 0.1hz to 300khz 685 2.5v internal reference f = 0.1hz to 10hz 21 f = 0.1hz to 10khz 159 f = 0.1hz to 300khz 705 4.096v internal reference f = 0.1hz to 10hz 26 f = 0.1hz to 10khz 213 f = 0.1hz to 300khz 750 reference input reference input range v ref 1.24 v dd v reference input current i ref v ref = v dd = 5.5v 55 74 f a reference input impedance r ref 75 100 k i ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 5 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units reference ouput reference output voltage v ref v ref = 2.048v, t a = +25 n c 2.043 2.048 2.053 v v ref = 2.5v, t a = +25 n c 2.494 2.5 2.506 v ref = 4.096v, t a = +25 n c 4.086 4.096 4.106 reference temperature coefficient q 10 q 25 ppm/ n c reference drive capacity external load 25 k i reference capacitive load 200 pf reference load regulation i source = 0 to 500 f a 2 mv/ma reference line regulation 0.05 mv/v power requirements supply voltage v dd v ref = 4.096v 4.5 5.5 v all other options 2.7 5.5 supply current (note 9) i dd internal reference, v dd = 5.5v v ref = 2.048v 0.85 1.25 ma v ref = 2.5v 0.9 1.25 v ref = 4.096v 1.1 1.40 external reference v dd = v ref = 3v 0.65 1.1 v dd = v ref = 5v 0.9 1.25 power-down mode supply current i pd all dacs off, internal reference on 140 f a all dacs off, internal reference off, t a = -40 n c to +85 n c 0.5 1 all dacs off, internal reference off, t a = +125 n c 1.2 2.5 digital input characteristics (scl, sda, addr) input high voltage v ih 2.7v < v dd < 5.5v 0.7 x v dd v input low voltage v il 2.7v < v dd < 5.5v 0.3 x v dd v hysteresis voltage v h 0.15 v input leakage current i in v in = 0v or v dd q 0.1 q 1 f a input capacitance (note 10) c in 10 pf addr pullup/pulldown strength r pu , r pd (note 11) 30 50 90 k i digital output (sda) output low voltage v ol i sink = 3ma 0.2 v ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 6 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 2: limits are 100% production tested at t a = +25c and/or t a = +125c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are at t a = +25c and are not guaranteed. note 3: dc performance is tested without load. note 4: linearity is tested with unloaded outputs to within 20mv of gnd and v dd . note 5: gain and offset tested at code 4065 and 30, respectively with v ref = v dd . note 6: subject to zero and full-scale error limits and v ref settings. note 7: measured with all other dac outputs at midscale with one channel transitioning 0 to full scale. note 8: on power-up, the device initiates an internal 200s (typ) calibration sequence. all commands issued during this time will be ignored. note 9: all channels active at v fs , unloaded. static logic inputs with v il = v gnd and v ih = v dd . note 10: guaranteed by design. note 11: an unconnected condition on the addr pin is sensed via a resistive pullup and pulldown operation; for proper operation, the addr pin should be tied to v dd , gnd, or left unconnected with minimal capacitance. parameter symbol conditions min typ max units i 2 c timing characteristics (scl, sda) scl clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 f s hold time repeated for a start condition t hd;sta 0.6 f s scl pulse width low t low 1.3 f s scl pulse width high t high 0.6 f s setup time for repeated start condition t su;sta 0.6 f s data hold time t hd;dat 0 900 ns data setup time t su;dat 100 ns sda and scl receiving rise time t r 20 + c b /10 300 ns sda and scl receiving fall time t f 20 + c b /10 300 ns sda transmitting fall time t f 20 + c b /10 250 ns setup time for stop condition t su;sto 0.6 f s bus capacitance allowed c b 10 400 pf pulse width of suppressed spike t sp 50 ns ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 7 figure 1. i 2 c serial interface timing diagram typical operating characteristics (t a = +25c, unless otherwise noted.) sda scl t buf t su;sto t r t sp t hd;sta t su;sta t f t high t su;dat t hd;dat t r t low t hd;sta t f s s s r p inl vs. code MAX5816 toc01 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load inl vs. code MAX5816 toc02 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load dnl vs. code MAX5816 toc03 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 8 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) dnl vs. code MAX5816 toc04 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load inl and dnl vs. supply voltage MAX5816 toc05 supply voltage (v) error (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 max inl v dd = v ref = 3v 1.0 -1.0 2.7 5.5 max dnl min dnl min inl inl and dnl vs. temperature MAX5816 toc06 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (lsb) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 max inl v dd = v ref = 3v max dnl min dnl min inl offset and zero-scale error vs. supply voltage MAX5816 toc07 supply voltage (v) error (mv) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.7 5.5 zero-scale error offset error v ref = 2.5v (external) no load offset and zero-scale error vs. temperature MAX5816 toc08 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (mv) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 v ref = 2.5v (external) no load offset error (v dd = 5v) offset error (v dd = 3v) zero-scale error full-scale error and gain-error vs. supply voltage MAX5816 toc09 supply voltage (v) error (%fs) 5.1 4.7 3.9 4.3 3.5 3.1 -0.016 -0.012 -0.008 -0.004 0 0.004 0.008 0.012 0.016 v ref = 2.5v (external) no load 0.020 -0.020 2.7 5.5 full-scale error gain error ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 9 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) full-scale error and gain error vs. temperature MAX5816 toc10 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (%fsr) -0.05 0 0.05 0.10 -0.10 v ref = 2.5v (external) no load gain error (v dd = 3v) gain error (v dd = 5v) full-scale error supply current vs. temperature MAX5816 toc11 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 supply current (ma) 0.6 0.8 1.0 1.4 1.2 0.4 out_ = full scale no load v ref (external) = v dd = 3v v ref (internal) = 2.048v, v dd = 5v v ref (internal) = 4.096v, v dd = 5v v ref (external) = v dd = 5v v ref (internal) = 2.5v, v dd = 5v supply current vs. supply voltage MAX5816 toc12 v dd (v) supply current (ma) 5.1 4.7 3.9 4.3 3.5 3.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 no load out_ = full scale t a = +25c 1.0 0 2.7 5.5 v ref (internal) = 4.096v v ref = 2.5v (external) v ref (internal) = 2.5v v ref (internal) = 2.048v, v dd = 5v power-down mode supply current vs. temperature MAX5816 toc13 supply voltage (v) 5.1 3.5 3.9 4.3 4.7 3.1 2.7 5.5 power-down supply current (ma) 0.4 0.8 1.6 1.2 0 power-down mode all dacs t a = -40c t a = +25c t a = +85c t a = +125c i vdd vs. code MAX5816 toc14 code (lsb) supply current (ma) 3584 3072 512 1024 1536 2048 2560 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 0 4096 v dd = 5v, v ref = 2.5v no load v dd = 5v, v ref = 4.096v v dd = v ref = 5v v dd = 5v, v ref = 2.048v v dd = v ref = 3v i ref (external) vs. code MAX5816 toc15 code (lsb) reference current (a) 3584 3072 2560 2048 1536 1024 10 20 30 40 50 60 0 512 0 4096 v dd = v ref no load v ref = 5v v ref = 3v MAX5816 toc16 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3.75s 1/4 scale to 3/4 scal e MAX5816 toc17 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div 4.3s settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3/4 scale to 1/4 scal e ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 10 ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) MAX5816 toc18 trigger pulse 5v/div 1 lsb change (midcode transition 0x800 to 0x7ff) glitch impulse = 2nv*s zoomed v out 1.25mv/div 2s/div major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) MAX5816 toc19 2s/div trigger pulse 5v/div zoomed v out 1.25mv/div 1 lsb change (midcode transition 0x7ff to 0x800) glitch impulse = 2nv*s v out vs. time transient exiting power-down MAX5816 toc20 dac output 500mv/div 10s / div v scl 5v/div 0v 36 th edge 0v v dd = 5v, v ref = 2.5v external power-on reset to 0v MAX5816 toc21 v out 2v/div 20s / div v dd 2v/div 0v 0v v dd = v ref = 5v 10ki load to v dd channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, r l = 2ki , c l = 200pf) MAX5816 toc22 4s / div trigger pulse 10v/div transitioning dac 1v/div static dac 1.25mv/div no load r l = 2ki transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.5nv*s channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, no load) MAX5816 toc23 5s / div trigger pulse 10v/div static dac 1.25mv/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 1.8nv*s transitioning dac 1v/div no load no load
maxim integrated products 11 ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, r l = 2ki , c l = 200pf) MAX5816 toc24 5s / div trigger pulse 10v/div static dac 1.25mv/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.3nv*s transitioning dac 1v/div no load r l = 2ki MAX5816 toc25 trigger pulse 10v/div static dac 1.25mv/div 4s/div channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, no load) transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 1.1nv*s transitioning dac 1v/div no load no load 0.1hz to 10hz output noise, external reference (v dd = 5v, v ref = 4.5v) MAX5816 toc31 2v/div midscale unloaded v p-p = 12v 4s /div output current limiting MAX5816 toc28 i out (ma) d v out (mv) 60 50 30 40 -10 0 10 20 -20 -400 -300 -200 -100 0 100 200 300 400 500 -500 -30 70 v dd = v ref v dd = 5v v dd = 3v MAX5816 toc26 50ns/div digital feedthrough (v dd = v ref = 5v, r l = 2ki , c l = 200pf) v out_ 1.65mv/div digital feedthrough = 0.1nv*s v dd = 5v v ref = 5v (external) dac at midscale headroom at rails vs. output current MAX5816 toc29 i out (ma) v out (v) 9 8 6 7 2 3 4 5 1 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 0 01 0 v dd = 5v, sourcing v dd = 3v, sourcing v dd = 3v and 5v sinking v dd = v ref dac = full scale output load regulation MAX5816 toc27 i o ut (ma) d v out (mv) 50 40 20 30 -10 0 10 -20 -8 -6 -4 -2 0 2 4 6 8 10 -10 -30 60 v dd = v ref v dd = 5v v dd = 3v noise-voltage density vs. frequency (dac at midscale) MAX5816 toc30 frequency (hz) noise-voltage density (nv/ hz) 10k 1k 50 100 150 200 250 300 350 0 100 100k v dd = 5v, v ref = 2.048v (internal) v dd = 5v, v ref = 4.5v (external) v dd = 5v, v ref = 4.096v (internal) v dd = 5v, v ref = 2.5v (internal)
maxim integrated products 12 ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.048v) MAX5816 toc32 2v/div midscale unloaded v p-p = 13v 4s /div supply current vs. input logic voltage MAX5816 toc37 input logic voltage (v) supply current (a) 4 3 2 1 200 400 600 800 1000 1200 0 05 v dd = 5v (ramp up) v dd = 5v (ramp down) v dd = 3v (ramp down) v dd = 3v (ramp up) 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.5v) MAX5816 toc33 2v/div midscale unloaded v p-p = 15v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 4.096v) MAX5816 toc34 2v/div midscale unloaded v p-p = 16v 4s /div v ref drift vs. temperature MAX5816 toc35 temperature coefficient (ppm/c) device count 12 11 1 2 3 5 6 7 8 9 4 10 1 2 3 4 5 6 7 8 0 0 v dd = 2.7v v ref = 2.5v box method reference load regulation MAX5816 toc36 reference output current (a) dv ref (mv) 450 400 350 300 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 -1.0 0 500 v dd = 5v internal reference v ref = 2.048v, 2.5v, and 4.096v
maxim integrated products 13 pin description pin configuration pin name function 1 outa buffered channel a dac output 2 outb buffered channel b dac output 3 gnd ground 4 outc buffered channel c dac output 5 outd buffered channel d dac output 6 addr i 2 c address selection input 7 scl supply voltage input. i 2 c interface clock input 8 sda i 2 c bidirectional serial data 9 v dd digital interface power-supply input. bypass with a 0.1f capacitor to gnd. 10 ref reference voltage input/output ep exposed pad. connect the exposed pad to ground. 1 3 4 10 8 7 ref sda scl MAX5816 2 9 v dd 5 + 6 addr outa gnd outc outb outd *ep tdfn top view ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 14 detailed description the MAX5816 is a 4-channel, low-power, 12-bit buff - ered voltage-output dac. the 2.7v to 5.5v wide supply voltage range and low-power consumption accommo - dates most low-power and low-voltage applications. the device presents a 100k i load to the external reference. the internal output buffers allow rail-to-rail operation. an internal voltage reference is available with software selectable options of 2.048v, 2.5v, or 4.096v. the device features a fast 400khz i 2 c-compatible interface. the MAX5816 includes a serial-in/parallel-out shift register, internal code and dac registers, a power-on-reset (por) circuit to initialize the dac outputs to code zero, and control logic. dac outputs (out_) the MAX5816 includes internal buffers on all dac out - puts. the internal output buffers provide improved load regulation for the dac outputs. the output buffers slew at 1v/ f s (typ) and drive up to 2k i in parallel with 500pf. under no-load conditions, the output buffers drive from gnd to v dd , subject to offset and gain errors. with a 2k load to gnd, the output buffers drive from gnd to within 200mv of v dd . with a 2k load to v dd , the output buffers drive to within 200mv of gnd and v dd . the dac ideal output voltage is defined by: out ref n d vv 2 = where d = code loaded into the dac register, v ref = reference voltage, n = resolution. internal register structure the user interface is separated from the dac logic to minimize digital feedthrough. within the serial interface is an input shift register, the contents of which can be routed to control registers, individual, or multiple dacs as determined by the user command. within each dac channel there is a code register followed by a dac latch register (see the detailed functional diagram ). the contents of the code register hold pending dac output settings which can later be loaded into the dac registers. the code register can be updated using both code and code_load user com - mands. the contents of the dac register hold the current dac output settings. the dac register can be updated directly from the serial interface using the code_load commands or can upload the current contents of the code register using load commands. the contents of both code and dac registers are main - tained during power-down states, so that when the dacs are powered on, they return to their previously stored output settings. any code or load commands issued during power-down states continue to update the reg - ister contents. sw_clear and sw_reset commands (both clear and reset modes) reset the contents of all code and dac registers to their zero-scale defaults. internal reference the MAX5816 includes an internal precision voltage ref - erence that is software selectable to be 2.048v, 2.500v, or 4.096v. when an internal reference is selected, that voltage is available on the ref pin for other external cir - cuitry (see figure 9 ) and can drive a 25k i load. external reference the external reference input has a typical input imped - ance of 100k i and accepts an input voltage from +1.24v to v dd . connect an external voltage supply between ref and gnd to apply an external reference. the MAX5816 powers up and resets to external reference mode. visit www.maxim-ic.com/products/references for a list of available external voltage-reference devices. i 2 c serial interface the MAX5816 features an i 2 c-/smbus k -compatible, 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl enable communication between the MAX5816 and the master at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the MAX5816 by transmitting the proper slave address followed by the command byte and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted to the MAX5816 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the MAX5816 must transmit the proper slave address followed by a series of nine scl pulses for each byte of data requested. the MAX5816 transmits data on sda in sync with the master-generated scl pulses. the master acknowledges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowledge, and a stop condition. sda operates as both an input and ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 15 an open-drain output. a pullup resistor, typically 4.7k i is required on sda. scl operates only as an input. a pullup resistor, typically 4.7k i , is required on scl if there are multiple masters on the bus, or if the single master has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the MAX5816 from high voltage spikes on the bus lines and mini - mize crosstalk and undershoot of the bus signals. the MAX5816 can accommodate bus voltages higher than v dd up to a limit of 5.5v; bus voltages lower than v dd are not recommended and may result in significantly increased interface currents. i 2 c start and stop conditions sda and scl idle high when the bus is not in use. a mas - ter initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high ( figure 2 ). a start condition from the master signals the beginning of a transmission to the MAX5816. the master terminates transmission and frees the bus, by issuing a stop condition. the bus remains active if a repeated start condition is gener - ated instead of a stop condition. i 2 c early stop and repeated start conditions the MAX5816 recognizes a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. transmissions ending in an early stop condition will not impact the internal device settings. if the stop occurs during a readback byte, the transmission is terminated and a later read mode request will begin transfer of the requested register data from the beginning (this applies to combined format i 2 c read mode transfers only, interface verification mode transfers will be corrupted). see figure 2 . i 2 c slave address the slave address is defined as the seven most sig - nificant bits (msbs) followed by the r/ w bit. see figure 4 . the five most significant bits are 00011 with the 2 lsbs determined by addr as shown in table 1 . setting the r/ w bit to 1 configures the MAX5816 for read mode. setting the r/ w bit to 0 configures the MAX5816 for write mode. the slave address is the first byte of information sent to the MAX5816 after the start condition. the MAX5816 has the ability to detect an unconnected state on the addr input for additional address flexibility; if leaving the addr input unconnected, be certain to minimize all loading on the pin (i.e. provide a landing for the pin, but do not allow any board traces). figure 2. i 2 c start, repeated start, and stop conditions table 1. i 2 c slave address lsbs for tdfn package addr a1 a0 v dd 0 0 n.c. 1 0 gnd 1 1 scl sda ss rp valid start, repeated start, and stop pulses ps p sp p s invalid start/s top pulse pairings -all will be recognized as starts ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 16 i 2 c broadcast address a broadcast address is provided for the purpose of updating or configuring all MAX5816 devices on a given i 2 c bus. all MAX5816 devices acknowledge and respond to the broadcast device address 00010000. the devices will respond to the broadcast address, regard - less of the state of the address pins. the broadcast mode is intended for use in write mode only (as indicated by r/ w = 0 in the address given). i 2 c acknowledge in write mode, the acknowledge bit (ack) is a clocked 9th bit that the MAX5816 uses to handshake receipt of each byte of data as shown in figure 3 . the MAX5816 pulls down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiv - ing device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master will retry communication. in read mode, the master pulls down sda during the 9th clock cycle to acknowledge receipt of data when the MAX5816 is in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to con - tinue. a not-acknowledge is sent when the master reads the final byte of data from the MAX5816, followed by a stop condition. i 2 c command byte and data bytes a command byte follows the slave address. a command byte is typically followed by two data bytes unless it is the last byte in the transmission. if data bytes follow the command byte, the command byte indicates the address of the register that is to receive the following two data bytes. the data bytes are stored in a temporary register and then transferred to the appropriate register during the ack periods between bytes. this avoids any glitch - ing or digital feedthrough to the dacs while the interface is active. i 2 c write operations (standard protocol) a master device communicates with the MAX5816 by transmitting the proper slave address followed by command and data words. each transmit sequence is framed by a start or repeated start condi - tion and a stop condition as described above. each word is 8 bits long and is always followed by an acknowledge clock (ack) pulse as shown in the figure 4 and figure 5 . the first byte contains the address of the MAX5816 with r/ w = 0 to indicate a write. the second byte contains the command (or register) to be written and the third and fourth bytes contain the data to be written. by repeating the com - mand plus data byte pairs (byte #2 through byte #4 in figure 4 and figure 5 ), the user can execute multiple command writes using a single i 2 c write sequence. there is no limit as to how many commands the user can execute with a single write sequence. the MAX5816 sup - ports this capability for all user-accessible write mode commands. figure 3. i 2 c acknowledge figure 4. i 2 c single register write sequence 1 scl start condition sda 29 clock pulse for acknowledgment acknowledge not acknowledge scl a 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 start sda write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) 21 22 23 stop 7 6 5 4 3 2 1 a 0 ack. generated by MAX5816 command executed 1 1 a a1 a0 w 0 0 0 ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 17 i 2 c write operation (multibyte operation) the MAX5816 supports a multibyte transfer protocol for some commands. in multibyte mode, once a command is issued (with multibyte bit = 1), that command is con - tinuously executed based on two byte data blocks for the duration i 2 c operation. essentially, bytes 1 to 4 are processed normally, but for every two bytes of data pro - vided after byte 4, the originally requested command is executed again with the latest byte pair provided as input data. multibyte protocol is enforced until a stop condi - tion (or repeated start) is encountered, this provides a higher speed transfer mode that is useful in servo dac applications. combined format i 2 c readback operations each readback sequence is framed by a start or repeated start condition and a stop condition. each word is 8 bits long and is followed by an acknowledge clock pulse as shown in figure 6 . the first byte contains the address of the MAX5816 with r/ w = 0 to indicate a write. the second byte contains the register that is to be read back. there is a repeated start condition, fol - lowed by the device address with r/ w = 1 to indicate a read and an acknowledge clock. the master has control of the scl line but the MAX5816 takes over the sda line. the final two bytes in the frame contain the register data readback followed by a stop condition. if additional bytes beyond those required to readback the requested data are provided, the MAX5816 will continue to read - back ones. readback of individual code registers is supported for all the user code commands. for these commands, which support a dac address, the requested channel code register content will be returned; if all dacs are selected, code a content will be returned. readback of individual dac registers is supported for all user load and code_load commands. for these commands, which support a dac address, the request - ed dac register content will be returned. if all dacs are selected, daca content will be returned. modified readback of the power register is supported for the power command. the power status of each dac is reported in locations b[3:0], with a 1 indicating the dac is powered down and a zero indicating the dac is operational (see table 2 ). readback of all other registers is not directly supported. all requests to read unsupported registers reads back the devices reference status device id and revision information in the format is shown in table 2 . interface verification i 2 c readback operations while the MAX5816 supports standard i 2 c readback of selected registers, it is also capable of functioning in an interface verification mode. this mode is accessed any time a readback operation follows an executed write mode command. in this mode, the last executed three- byte command is read back in its entirety. this behavior allows verification of the interface. sample command sequences are shown in figure 7 . the first command transfer is given in write mode with r/ w = 0 and must be run to completion to qualify for interface verification readback. there is now a stop/start pair or repeated start condition required, followed by the readback transfer with r/ w = 1 to indicate a read and an acknowledge clock from the MAX5816. the master still has control of the scl line but the MAX5816 takes over the sda line. the final three bytes in the frame contain the command and register data written in the first transfer presented for readback, followed by a stop condition. if additional bytes beyond those required to read back the requested data are provided, the MAX5816 will continue to read back ones. table 2. standard i 2 c user readback data command byte (request) readback data high byte readback data low byte r7 r6 r5 r4 r3 r2 r1 r0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 x 0 0 0 a2 a1 a0 coden[11:4] coden[3:0] 0 0 0 0 0 x 0 0 1 a2 a1 a0 dacn[11:4] dacn[3:0] 0 0 0 0 0 x 0 1 0 a2 a1 a0 dacn[11:4] dacn[3:0] 0 0 0 0 0 x 0 1 1 a2 a1 a0 dacn[11:4] dacn[3:0] 0 0 0 0 0 x 1 0 0 x x x 0 0 0 0 0 0 0 0 0 0 0 0 pwd pwc pwb pwa 0 x 1 0 1 x x x 1 0 0 0 1 0 0 0 0 1 0 rev_id [2:0] (010) ref mode [1:0] 0 x 1 1 0 x x x 0 x 1 1 1 x x x ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 18 figure 6. i 2 c multibyte register write sequence (multibyte protocol) figure 7. standard i 2 c register read sequence figure 5. multiple register write sequence (standard i 2 c protocol) scl a w n n n n a n d d d d d d d a d start sda n 0 0 0 1 1 a1 a0 1 0 stop d d d d d d d a d d d d d d d d a d d d d d d d d a d ack. generated by i 2 c master ack. generated by MAX5816 reg n updated reg n updated write address byte #1: device address write register no. byte #2: first reg# = n write data byte #3: reg(n)[15:8] data write data byte #4: reg(n)[7:0] data additional data byte pairs (2 byte blocks) write data byte #x-1: reg(n)[15:8] data write data byte #x: reg(n)[7:0] data a a read data byte #4: data 1 high byte (b[15:8]) read data byte #5: data 1 low byte (b[7:0]) repeated start read address byte #3: i 2 c slave address write address byte #1: i 2 c slave address write command 1 byte #2: command 1 byte ack. generated by MAX5816 ack. generated by i 2 c master a a start stop scl sda 00 01 1a 1a 0w aa 0 0n 0 00 11 a1 a0 ra d ddd dd dd dddddddd ~a a nn nnn scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 start sda write address byte #1: i 2 c slave address write command1 byte #2: command1 byte (b[23:16]) write data1 byte #3: data1 high byte (b[15:8]) 21 0 0 0 1 1 a1 a0 22 23 stop 7 6 5 4 3 2 1a 0 write data1 byte #4: data1 low byte (b[7:0]) 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 21 22 23 7 6 5 4 3 2 1a 0 additional command and data pairs (3 byte blocks) command1 executed commandn executed byte #5: commandn byte (b[23:16]) byte #6: datan high byt e (b[15:8]) byte #7: datan low byt e (b[7:0]) ack. generated by MAX5816 a ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 19 figure 8. interface verification i 2 c register read sequences scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9 a 8 sda 0 0 0 1 1 a1 a0 22 23 7 6 5 4 3 2 1 a 0 r ~a pointer updated (qualifies for combined read back) command executed (qualifies for interface read back) scl sda command executed (qualifies for interface read back) pointer updated (qualifies for combined read back) 21 a w2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 01 1a 1a 02 2 23 76 54 32 1a 0 21 start stop write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) start stop write address byte #1: i 2 c slave address read command byte #2: command byte (b[23:16]) read data byte #3: data high byte (b[15:8]) read data byte #4: data low byte (b[7:0]) start repeated start write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) stop write address byte #1: i 2 c slave address read command byte #2: command byte (b[23:16]) read data byte #3: data high byte (b[15:8]) read data byte #4: data low byte (b[7:0]) ack. generated by MAX5816 ack. generated by i 2 c master a2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 01 1a 1a 02 2 23 76 54 32 10 21 a r2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 01 1a 1a 02 2 23 76 54 32 1~ a 0 21 a a ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 20 it is not necessary for the write and read mode transfers to occur immediately in sequence. i 2 c transfers involving other devices do not impact the MAX5816 readback mode. toggling between readback modes is based on the length of the preceding write mode transfer. combined format i 2 c readback operation is resumed if a write command greater than two bytes but less than four bytes is supplied. for commands written using multiple register write sequences, only the last command executed is read back. for each command written, the readback sequence can only be completed one time; partial and/or multiple attempts to readback executed in succession will not yield usable data. i 2 c compatibility the MAX5816 is fully compatible with existing i 2 c sys - tems. scl and sda are high-impedance inputs; sda has an open drain which pulls the data line low to transmit data or ack pulses. figure 9 shows a typical i 2 c appli - cation. i 2 c user-command register map this section lists the user accessible commands and registers for the MAX5816. table 3 provides detailed information about the command registers. figure 9. typical i 2 c application circuit c addr scl sda scl sda addr +5v scl sda MAX5816 MAX5816 ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 21 table 3. i 2 c commands summary command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description dac commands coden 0 0 0 0 0 dac address code register data [11:4] code register data [3:0] x x x x writes data to the selected code register(s). loadn 0 0 0 0 1 dac address x x x x x x x x x x x x x x x x transfers data from the selected code registers to the selected dac register(s). coden_ load_ all 0 0 0 1 0 dac address code register data [11:4] code register data [3:0] x x x x simultaneously writes data to the selected code register(s) while updating all dac registers. coden_ loadn 0 0 0 1 1 dac address code register data [11:4] code register data [3:0] x x x x simultaneously writes data to the selected code register(s) while updating selected dac register(s). ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 22 table 3. i 2 c commands summary (continued) command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description configuration commands power 0 x 1 0 0 x x x x x x x x x x x x x power mode 00 = normal 01 = pd 1k i 10 = pd 100k i 11 = pd hi-z dac d dac c dac b dac a sets the power mode of the selected dacs (dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted). sw_ reset or sw_ clear 0 x 1 0 1 x x x x x x x x x x x x x x x x x x 0 = clr 1 = rst executes a software reset (all registers returned to their default values) or clear (all code and dac registers cleared to their default values). config 0 x 1 1 0 x x x x x x x x x x x x x x x dac d dac c dac b dac a sets the dac latch mode of the corresponding dac: 0 = dac latch is load controlled 1 = dac latch is transparent. ref 0 x 1 1 1 x x x x x x x x x x x x x x x x ref pow-er mode ref mode 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.1v sets the reference operating mode. ref power (b2): 0 = internal reference is only powered if at least one dac is powered 1 = internal reference is always powered. ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 23 table 3. i 2 c commands summary (continued) command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description multibyte dac commands coden multibyte 0 1 0 0 0 dac address code register data[11:4] code register data[3:0] x x x x writes data to the selected code register(s) (multibyte variant). loadn multibyte 0 1 0 0 1 dac address x x x x x x x x x x x x x x x x transfers data from the selected code registers to the selected dac register(s) (multibyte variant). coden_ load_ all multibyte 0 1 0 1 0 dac address code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the selected code register(s) while updating all dac registers (multibyte variant). coden_ loadn multibyte 0 1 0 1 1 dac address code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the selected code register(s) while updating selected dac register(s) (multibyte variant). ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 24 coden command the coden command updates the code register contents for the selected dac(s). changes to the code register content based on this command will not affect dac outputs directly unless the latch has been configured to be trans - parent (see the config command). in order to update code register content of all dacs, use the coden command with dac selection = 1xx = all dacs. the coden command supports the multibyte protocol. see table 3 and table 5 . table 5. coden (000) command format table 6. loadn (001) command format loadn command the loadn command (b[23:20] = 0001) updates the dac register content for the selected dac(s) by uploading the current contents of the code register. the loadn command can be used with dac selection = 1xx = all dacs to issue a software load for all dacs, which does not alter the existing content of any code register (unlike coden_ load_all command). see table 3 and table 6 . the loadn command supports the multibyte protocol. table 4. dac selection b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 m 0 0 0 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x reserved multibyte coden command dac address code register data [11:4] code register data [3:0] dont care data default value ? 0 0 0 0 0 0 0 0 0 0 0 0 x x x x command byte data high byte data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 m 0 0 1 a2 a1 a0 x x x x x x x x x x x x x x x x reserved multibyte loadn command dac address dont care dont care command byte data high byte data low byte b18 b17 b16 dac selected 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 x x all dacs ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 25 table 7. codenloadall (010) command format table 8. codenloadn (011) command format coden_load_all command the coden_load_all command updates the code register contents for the selected dac(s) as well as the dac register content of all dacs. channels for which the code register content has not been modified since the last load to dac register will not be updated to reduce digital crosstalk. the coden_load_all command by definition will modify at least one code register. to avoid this, use the loadn command with dac selection = all dacs. the coden_load_all command supports the multibyte protocol. see table 3 and table 7 . coden_loadn command the coden_loadn command updates the code register contents for the selected dac(s) as well as the dac register content of the selected dac(s). channels for which the code register content have not been modified since the last load to dac register will not be updated to reduce digital crosstalk. see table 3 and table 8 . b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 m 0 1 0 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x reserved multibyte coden_ load_ all command dac address code register data[11:4] code register data [3:0] dont care data default value ? 0 0 0 0 0 0 0 0 0 0 0 0 x x x x command byte data high byte data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 m 0 1 1 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x reserved multibyte coden_loadn command dac address code register data [11:4] code register data [3:0] dont care data default value ? 0 0 0 0 0 0 0 0 0 0 0 0 x x x x command byte data high byte data low byte ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 26 table 9. power (100) command format table 10. swreset (101) command format power command the MAX5816 features a software-controlled power- mode (power) command. the power command updates the power-mode settings of the selected dacs while the power settings of the remaining of the dacs remain unchanged. the new power setting is determined by bits b[5:4] while the affected dac(s) are selected by bits b[3:0]. if all dacs are powered down, the device enters a standby mode. in power-down, the output is disconnected from the buffer and is grounded when one of the two selectable internal resistors or set to high impedance. see table 9 for the selectable internal resistor values in power-down mode. in standby mode, the dac register retains its value so that the output is restored when the device pow - ers up. the serial interface remains active in power-down mode. in powered down mode, the internal reference can be powered down or it can be set to remain powered-on for external use in standby mode, parts using external reference do not load the ref. see table 9 . sw_reset and sw_clear command the sw_reset and sw_clear commands provide a means of issuing a software reset or software clear operation. set b0 = 0 to issue a software clear operation to return all code and dac registers to the zero-scale value. set b0 = 1 to reset all code, dac, and configura - tion registers to their default values. see table 10 . b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 x 1 0 0 x x x x x x x x x x x x x pd1 pd0 d c b a reserved dont care power command dont care dont care dont care power mode: 00 = normal mode 01 = 1k i 10 = 100k i 11 = hi-z dac selection data default value ? x x x x x x x x x x 0 0 1 1 1 1 command byte data high byte data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 x 1 0 1 x x x x x x x x x x x x x x x x x x r0 reserved dont care sw_reset or sw_clear command dont care dont care dont care 0 = clear 1= reset data default value ? x x x x x x x x x x x x x x x 1 command byte data high byte data low byte ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 27 table 11. config command format table 12. ref command format config command the config command allows independent configurations of the dac. in normal mode (0), the dac latch is operational and responds to load commands. in transparent mode (1), the dac latch is transparent and code register contents are supplied directly to the dac outputs. see table 11 . ref command the ref command updates the global reference setting used for all dac channels. set b[1:0] = 00 to use an external reference for the dacs or set b[1:0] to 01, 10, or 11 to select either the 2.500v, 2.048v, or 4.096v internal reference, respectively. if rf2 (b2 = 0) is set to zero (default) in the ref command, the reference will be powered down any time all dac chan - nels are powered down (in standby mode). if rf2 is set to one, the reference will remain powered even if all dac channels are powered down, allowing continued operation of external circuitry. in this mode the 1a shutdown state is not available. see table 12 . b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 x 1 1 1 x x x x x x x x x x x x x x x x rf2 rf1 rf0 reserved dont care ref command dont care dont care dont care 0 = default 1 = always on ref mode: 00 = ext 01 = 2.500v 10 = 2.048v 11 = 4.096v data default value ? x x x x x x x x x x x x x 0 0 0 command byte data high byte data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 x 1 1 0 x x x x x x x d c b a x x x x d c b a reserved dont care config command dont care dont care dont care dac latch mode 0 = operational 1 = transparent data default value ? x x x x x x x x x x x x 0 0 0 0 command byte data high byte data low byte ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 28 applications information power-on reset (por) when power is applied to v dd , the dac output is set to zero scale. to optimize dac linearity, wait until the sup - plies have settled and the internal setup and calibration sequence completes (200 f s, typ). note all commands issued during the period will be ignored. power supplies and bypassing considerations bypass v dd with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device. minimize lead lengths to reduce lead inductance. connect the gnd to the analog ground plane. layout considerations digital and ac transient signals on gnd can create noise at the output. connect gnd to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the MAX5816 gnd. carefully layout the traces between channels to reduce ac cross-coupling. do not use wire- wrapped boards and sockets. use shielding to minimize noise immunity. do not run analog and digital signals parallel to one another, especially clock signals. avoid routing digital lines underneath the MAX5816 package. definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl p 1 lsb, the dac guarantees no missing codes and is monotonic. if the magnitude of the dnl r 1 lsb, the dac output may still be monotonic. offset error offset error indicates how well the actual transfer func - tion matches the ideal transfer function at a single point. typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a transition, until the dac output settles to the new output value within the converters specified accuracy. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse a major carry transition occurs at the midscale point where the msb changes from low to high and all other bits change from high to low, or where the msb changes from high to low and all other bits change from low to high. the duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. the digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 29 detailed functional diagram outa buffer a dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register a dac latch a 12 - bit dac a outb buffer b dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register b dac latch b 12 - bit dac b outc buffer c dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register c dac latch c 12 - bit dac c outd buffer d dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register d dac latch d 12 - bit dac d addr sda scl por i 2 c serial interface ref 100ki r in internal/ external reference (user option) MAX5816 v dd gnd ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 30 typical operating circuit figure 10. bipolar operating circuit dac micro- controller sda scl addr out_ gnd v dd ref 100f 100nf note: unipolar operation (one channel shown) 4.7f r pu = 5ki r pu = 5ki MAX5816 dac micro- controller sda scl addr out gnd v dd ref 100f 100nf 4.7f r pu = 5ki r1 r2 r1 = r2 MAX5816 power supply (2.7v to 5.5v) ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim integrated products 31 ordering information note: the device is specified over the -40c to +125c temperature range. +denotes a lead(pb)Cfree/rohs-compliant package. t = tape and reel. *ep = exposed pad. chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part pin-package resolution (bit) internal reference tempco (ppm/ n c) MAX5816atb+t 10 tdfn-ep* 12 10 (typical) package type package code outline no. land pattern no. 10 tdfn-ep t1033+1 21-0137 90-0003 ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 32 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/12 initial release ultra-small, quad-channel, 12-bit buffered output dac with internal reference and i 2 c interface MAX5816

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